Library UNISIM;
use UNISIM.vcomponents.all;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity OutputBlock is
  Port( Device0data : inout std_logic_vector(15 downto 0);
        Device0i2cClk : inout std_logic;
        Device0i2cData : inout std_logic;
        
        Device1data : inout std_logic_vector(15 downto 0);
        Device1i2cClk : inout std_logic;
        Device1i2cData : inout std_logic;
        
        MasterData : inout std_logic_vector(15 downto 0);
        MasterI2CClk : inout std_logic;
        MasterI2CData : inout std_logic);
end OutputBlock;
